1. Field of the Invention
The present invention relates to eliminating the metastability in a circuit which is used to synchronize an asynchronous digital data signal, or the like, with a network driven by a system clock (synchronous). In particular, a level sensitive portion is added to the synchronizing circuit which ensures a definite binary voltage level is output to the synchronous network.
2. Description of Related Art
Typically, a latch, or register, is used to synchronize a data signal from a first clock domain into a second clock domain, where the first clock domain is asynchronous to the second. The register receives the asynchronous data signal from the first clock domain, but does not output the signal to the second clock domain, until its system clock transitions.
Generally, metastability is an event which causes a bi-stable element to require an indeterminate amount of time to generate a valid output. Metastability may occur when the data signal, input to the register, and the system clock (also input to the register) transition at nearly the same point in time. When this occurs, the circuitry does not have enough energy to drive the output signal to either a definite "high" (logical 1) or "low (logical 0). Logical 1 is the presence of a voltage, which may be 5, volts, 3.3 volts, 2.5 volts, or the like, depending on the type of circuit technology. Logical 0 is defined as the absence of a voltage, or ground potential, i.e. 0 volts. Since, during metastability, the energy level is insufficient to cause a definitive value to be output by the register, the output voltage can hover, or oscillate, between logical 0 and logical 1 for an extended period of time before resolving itself to high or low. Theoretically, the metastable state could be maintained indefinitely, however in reality external forces, such as electrical noise will cause the output to settle at either the high level or low level within a definable time period.
The instability of the output signal can cause other portions of the system to become unstable and give incorrect results, cause the system to crash, or even damage other components in the system.
Types of signals that may require synchronization with the system clock can include asynchronous communication signals inputs form a modem, keyboard or other user interface, analog to digital (A/D) converters, multiport memories, or the like. As microprocessor manufacturers build systems with increasingly faster clock speeds, the possibility that an asynchronous data signal and the system clock signal (both input to a synchronizing register) will transition at, or near the same time, becomes more likely to occur, with metastability being the result.
Conventional systems have been developed which use multiple synchronizer stages and multiple cycle synchronizers. With multiple synchronizer stages, additional registers are added to receive the asynchronous signal. This decreases the probability that a metastable condition will ever occur, since the output of the first register will have to be in a metastable condition when it is input to a second register, and so forth. This conventional solution is based on the probability of a metastable condition continuing for two or more clock periods is relatively small. Multiple cycle synchronizers slows down the clock rate to allow the registers more time to resolve a metastable output. The asynchronous input is sampled at a slower clock rate by dividing the system clock by N, using a 1/N divider circuit.
The multiple synchronizer stage technique requires additional register(s), which increase the system overhead by adding complexity that impacts performance. The conventional multiple cycle synchronizer intentionally slows the clock speed which also degrades performance. Further, each of these conventional approaches address the issue of trying to prevent metastability, rather than providing a definitive output value, independent of the occurrence of a metastable condition. Therefore, it can be seen that need exists for a solution to the metastability problem that ensures a definite voltage level output, regardless of whether the asynchronous data input signal and system clock signal transition at, or near the same time.